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| 1 GHz QUADRATURE MODULATOR FEATURES * DIRECT MODULATION RANGE: 800 MHz TO 1 GHz * SUPPLY VOLTAGE RANGE: VCC = 2.7 V to 3.6 V * LOW OPERATION CURRENT: 24 mA TYP * LOW CURRENT SLEEP MODE UPC8110GR FUNCTIONAL BLOCK DIAGRAM LO 0 RF OUT I I 90 Q Q DESCRIPTION The UPC8110GR is a silicon monolithic integrated circuit designed as a 1 GHz direct quadrature modulator for digital mobile communication systems. The device is manufactured using the NESAT III MMIC process and is housed in a 20 pin plastic SSOP package that contributes to miniaturizing the system. The device has power save function and operates on a 3 V supply voltage for low power consumption. NEC's stringent quality assurance and test procedures ensure the highest reliability and performance. ELECTRICAL CHARACTERISTICS (TA = 25C, VCC = 3 V, VPS 2.2 V PART NUMBER PACKAGE OUTLINE SYMBOLS ICC Po(SAT) LOL IMR IM3 I/Q ZI/QIN TPS (RISE) TPS (FALL) PARAMETERS AND CONDITIONS Circuit Current (no signal) VPS 2.2 V Circuit Current (power save) VPS 0.5 V Maximum Output Power1 LO Carrier Image Leak1 UNITS mA A dBm dBc dBc Distortion1 dBc k s s unless otherwise specified) UPC8110GR S20 MIN 20 -13 TYP 24 -10 -35 -40 -45 150 3 2 5 5 -30 -30 -30 MAX 33 10 Rejection1 I/Q 3rd Order Intermodulation I/Q Input Impedance, single-ended Power Save Rise Time, VPS 0.5 V to VPS 2.2 V Power Save Fall Time, VPS 2.2 V to VPS 0.5 V Note: 1. fLOIN = 948 MHz, PLOIN = -10 dBm, f I/Q = 2.625 kHz, V I/Q = VCC/2 (DC)+ 0.5 V p-p (AC). California Eastern Laboratories UPC8110GR ABSOLUTE MAXIMUM RATINGS1 (TA = 25C) SYMBOLS VCC VPS PD TOP TSTG PARAMETERS Supply Voltage Power Save Voltage Power Dissipation2 Operating Temperature Storage Temperature UNITS V V mW C C RATINGS 4.0 4.0 430 -40 to +85 -55 to +150 RECOMMENDED OPERATING CONDITIONS SYMBOLS VCC VPS TOP PLO fLOIN fI/QIN VI/QIN PARAMETERS Supply Voltage Power Save Voltage Operating Temperature LO Input Power Level LO Input Frequency I/Q Input Frequency I/Q Input Voltage UNITS MIN V V C dBm MHz MHz mVp-p mVp-p Notes: 1. Single-ended Input. 2. Differential Input. Equivalent Circuit 2.7 0 -40 -15 800 DC +25 -10 900 TYP 3.0 MAX 3.6 VCC +85 -7 1000 10 5001 2502 Notes: 1. Operation in excess of any one of these parameters may result in permanent damage. 2. Mounted on a 50 x 50 x 1.6 mm double copper clad epoxy glass PWB (TA = +85C). PIN FUNCTIONS Pin No. Symbol Supply Voltage (V) -- Pin Voltage (V) 2.6 Description 1 LOIN LO input for the phase shifter. 1 3 2 GND 0 -- Connect to ground with minimum inductance. Track length should be kept as short as possible. Bypass of the LO input. This pin is grounded through a capacitor of approx. 30 pF. Connect to ground with minimum inductance. Track length should be kept as short as possible. Input for Q signal. If the I/Q input signals are single-ended, the maximum amplitude of the signal is 500 mVp-p. Input for Q signal. If the I/Q input signals are single-ended, Q should be DC biased at VCC/2. If the I/Q input signals are differential, the maximum amplitude of the signal is 250 mVp-p. Input for I signal. If the I/Q input signals are single-ended, I should be DC biased at VCC/2. If the I/Q input signals are differential, the maximum amplitude of the signal is 250 mVp-p. Input for I signal. If the I/Q input signals are single-ended, the maximum amplitude of the signal is 500 mVp-p. Connect to ground with minimum inductance. Track length should be kept as short as possible. 5 6 3 LOIN -- 2.6 4 GND 0 -- 5 Q VCC/2*1 -- 6 Q VCC/2*1 -- 7 I VCC/2*1 -- 7 8 8 I VCC/2*1 -- 9 GND 10 0 -- 11 RFOUT -- 1.6 Output from the modulator. This is an emitter follower output. Connect approx. 15 in series to match to 50. 11 UPC8110GR PIN FUNCTIONS Pin No. 12 GND 13 0 -- Symbol Supply Voltage Pin Voltage Description Equivalent Circuit Connect to ground with minimum inductance. Track length should be kept as short as possible. Supply voltage pin for the modulator. An internal regulator helps keep the device stable against temperature or VCC variations. Connect to ground with minimum inductance. Track length should be kept as short as possible. Power save control pin can control the ON/SLEEP state with a bias as follows: VPS (V) 2.0 ~ 3.6 0 ~ 0.8 STATE ON SLEEP 14 15 VCC 2.7~ 3.6 -- GND 16 0 -- 17 Power Save VPS -- 17 18 GND 0 -- Connect to ground with minimum inductance. Track length should be kept as short as possible. Supply voltage pin for the modulator. An internal regulator helps keep the device stable against temperature or VCC variations. Connect to ground with minimum inductance. Track length should be kept as short as possible. 19 VCC 2.7 ~ 3.6 -- 20 GND 0 -- *1: VCC/2 DC bias must be supplied to I, I, Q, Q. TYPICAL PERFORMANCE CURVES Unless Otherwise Specified, (TA = +25C, VCC = VPS = 3 V, I/Q DC offset = 1.5 V, I/Q Input Signal = 500 mVp-p (Single ended), fI/Q = 2.625 kHz, fLOIN = 948 MHz, PLOIN = -10 dBm, CURRENT vs. VOLTAGE 30 TA = +25C TA = -40C TA = +85C VCC = VPS I/Q (DC) = VCC/2 RF None CURRENT vs. POWER SAVE VOLTAGE 30 TA = +25C TA = -40C TA = +85C VCC = 3 V I/Q (DC) = 1.5 V RF None 25 25 Cuurent, ICC (mA) Cuurent, ICC (mA) 20 20 15 15 10 10 5 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Voltage, VCC (V) Power Save Voltage, VPS (V) UPC8110GR TYPICAL PERFORMANCE CURVES Unless Otherwise Specified, (TA = +25C, VCC = VPS = 3 V, I/Q DC offset = 1.5 V, I/Q Input Signal = 500 mVp-p (Single ended), fI/Q = 2.625 kHz, fLOIN = 948 MHz, PLOIN = -10 dBm, 0 LOCAL INPUT FREQUENCY vs. PRFOUT, LOL, IMR, IM3I/Q Local Leak, LOL - ImageRejection, IMR - IM3I/Q (dBc) RF Output Power, PRFOUT (dBm) PRFOUT -35 LOL -40 IM3I/Q -45 -20 -15 -10 -5 -10 -15 -20 -50 -25 -25 100 200 300 400 500 -55 ImR -30 800 900 1000 1100 700 I/Q Input Signal, PI/QIN (mVP-P) LOCAL INPUT POWER vs. PRFOUT, LOL, IMR, IM3I/Q Local Input Frequency, fLO (MHz) I/Q BIAS VOLTAGE vs. PRFOUT, LOL, IMR, IM3I/Q Local Leak, LOL - ImageRejection, IMR - IM3I/Q (dBc) Local Leak, LOL - ImageRejection, IMR - IM3I/Q (dBc) -30 PRFOUT -35 LOL -40 ImR -45 -5 -30 PRFOUT -35 -5 RF Output Power, PRFOUT (dBm) -10 -10 -15 -40 LOL ImR -15 -20 -45 -20 -50 IM3I/Q -25 -50 IM3I/Q -25 -55 -15 -10 -5 -30 -55 -15 -10 -5 -30 Local Input Power, LO (dBm) I/Q Supply Voltage,I/Q (DC) (V) TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM REF 0.0 dBm ATT 1OdB A_write B_blank POUT MARKER -10.50 kHz TYPICAL /4DQPSK MODULATION OUTPUT SPECTRUM ATT 1OdB A_write B_blank MARKER -10.50 kHz -47.36 dB REF Level 0 dBm 10 dB/ LOL 1 IM3I/Q ImR 3 2 2 ADJ BS 21 kHz RBW 3 kHz VBW 3 kHz SWP 5 s 3 1 4 RBW 300Hz VBW 300 Hz SWP 1.2 s CENTER 948.00000 MHz SPAN 50.0 kHz CENTER 948.00000 MHz SPAN 50.0 kHz Padj (dB) Marker No. 1: 947.90 MHz No. 2: 947.95 MHz No. 1: 948.05 MHz No. 2: 948.10 MHz -78.0 dB -67.0 dB -70.3 dB -77.8 dB f = -100 kHz f = -50 kHz f = +50 kHz f = +100 kHz RF Output Power, PRFOUT (dBm) RF Output Power, PRFOUT (dBm) VCC = 3.0 V Single ended -30 -5 UPC8110GR TYPICAL PERFORMANCE CURVES Unless Otherwise Specified, (TA = +25C, VCC = VPS = 3 V, I/Q DC offset = 1.5 V, I/Q Input Signal = 500 mVp-p (Single ended), fI/Q = 2.625 kHz, fLOIN = 948 MHz, PLOIN = -10 dBm, POWER SAVE RESPONSE (at VCC = VPS = 2.7 V) REF 0.0 dBm 10 dB/ MARKER 2.714 s ATT 1OdB A_view B_blank MARKER 2.714 s 44.41 dB REF 0.0 dBm 10 dB/ MARKER 2.714 s POWER SAVE RESPONSE (at VCC = VPS = 3.0 V) ATT 1OdB A_view B_blank MARKER 2.714 s 48.97 dB RBW 3 MHz VBW 3 MHz SWP 50 s CENTER 948.002642 MHz SPAN 0 Hz RBW 3 MHz VBW 3 MHz SWP 50 s CENTER 948.002642 MHz SPAN 0 Hz POWER SAVE RESPONSE (at VCC = VPS = 3.6 V) REF 0.0 dBm 10 dB/ MARKER 2.714 s ATT 1OdB A_view B_blank MARKER 2.714 s 45.97 dB RBW 3 MHz VBW 3 MHz SWP 50 s CENTER 948.002642 MHz SPAN 0 Hz SCATTERING PARAMETERS (TA = +25C) LO INPUT IMPEDANCE (LOIN) (at VCC = VPS = 3.0 V) 1: 30.191 7.1309 1.872 nH 948.000 000 MHz MARKER 1 948 MHz MARKER 1 948 MHz RF OUTPUT IMPEDANCE (RFOUT) (at VCC = VPS = 3.0 V) 1: 45.005 -2.6352 1.872 nH 948.000 000 MHz 1 1 START 700.000 000 MHz STOP 1 100.000 000 MHz START 700.000 000 MHz STOP 1 100.000 000 MHz UPC8110GR EXPLANATION OF INTERNAL FUNCTIONS Block Function/Operation Block Diagram from LO1in 90 PHASE SHIFTER Input signal from the LO input is sent to a T-type flip-flop through a frequency doubler. The output signal from the T-type F/F is changed to the same frequency as the LO input with a quadrature phase shift of 0, 90, 180, or 270. These circuits provide self phase correction for proper quadrature signals. x2 .2 F/F . BUFFER AMPLIFIER Buffer amplifiers for each phase signal are sent to each mixer. MIXER The signals from the buffer amps are quadrature modulated with two doublebalanced mixers. High accurate phase and amplitude inputs are realized to provide excellent image rejection. I I Q Q ADDER Output signals from each mixer are added and sent through a final amplifier. To MODout OUTLINE DIMENSIONS (Units in mm) PACKAGE OUTLINE S20 (SSOP20) 20 11 INTERNAL BLOCK DIAGRAM TOP VIEW 1 90 Phase Shifter REG. 20 LOIN GND VCC GND VPS (POWER SAVE) GND GND VCC GND GND RF OUT N NEC C8110G XXXXX 7.00 MAX 10 GND 2 19 XXX = Lot/Date Code LOIN GND 3 18 4 17 1 6.40.2 1.00.1 4.40.1 Q INPUT Q INPUT I INPUT 5 16 1.5 0.1 1.8 MAX +0.10 0.22 - 0.05 +0.10 0.15 -0.05 6 15 7 14 0.50.2 0.65 0.575 MAX Note: All dimensions are typical unless otherwise specified. I INPUT GND GND 8 9 10 13 12 11 ORDERING INFORMATION PART NUMBER UPC8110GR-E1 QTY 2.5 K/Reel EXCLUSIVE NORTH AMERICAN AGENT FOR RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS CALIFORNIA EASTERN LABORATORIES * Headquarters * 4590 Patrick Henry Drive * Santa Clara, CA 95054-1817 * (408) 988-3500 * Telex 34-6393 * FAX (408) 988-0279 24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) * Internet: http://WWW.CEL.COM DATA SUBJECT TO CHANGE WITHOUT NOTICE 09/14/2000 |
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